AES加密的资源优化设计及FPGA实现  

Resource Optimization of Advanced Encryption Standard and Its Implementation for FPGA

作　　者：殷伟凤[1] 

机构地区：[1]浙江传媒学院电子信息学院,浙江杭州310018

出　　处：《计算机与现代化》2012年第11期145-148,189,共5页Computer and Modernization

摘　　要：针对目前广泛应用的低功耗低速嵌入式设备,以减少面积为目标,本文给出一个精简的实现AES加密算法的硬件结构。在字节置换模块的设计中,改进采用查找表的方法而只用组合逻辑实现,采用将GF(28)域中的元素映射为复合域GF(24)来求逆的方法,大量减少资源占用;对混合列计算进行优化设计;最后,采用Altera的Cyclone芯片基于VHDL语言实现AES加密算法,并给出仿真结果。This paper presents a compact hardware architecture for the AES algorithm which aims at reducing hardware resources without using a memory.The architecture only requires one combined S-box for encryption,decryption and key expansion which implements the multiplicative inverse in the composite field GF（24）.In addition,the optimized combined MixColumns module has a lower gate count than other designs that implement mix columns operation.VHDL code is developed for the implementation of 128-bit data encryption with Device Cyclone of Altera Family.

关 键 词：对称块加密 RIJNDAEL算法 高级加密标准 高斯域 

分 类 号：TP309[自动化与计算机技术—计算机系统结构] TP368.1[自动化与计算机技术—计算机科学与技术]