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机构地区:[1]清华大学计算机科学与技术系,北京100084 [2]清华大学微电子学研究所,北京100084
出 处:《计算机辅助设计与图形学学报》2012年第11期1506-1512,共7页Journal of Computer-Aided Design & Computer Graphics
基 金:国家自然科学基金(61106031;61076034);清华大学自主科研计划
摘 要:针对电路后仿中大规模、多端口RC矩阵在降阶时非零元会显著增加,导致降阶系统处理时间大幅上升的问题,提出了寻找最优剩余节点数,使降阶后的网络求解速度达到最优的算法.首先采用统计建模的方法得到RC网络求解时间与节点数、非零元数的近似关系;然后在对实际电路进行模型降阶时用节点消去法快速得到剩余节点数与非零元的关系,从中选出最优的剩余网络节点数并根据它实施模型降阶.实验结果表明,采用该策略得到的降阶网络不造成精度损失,且使电路求解速度比已有方法快2~5倍.Model order reduction (MOR) has been widely used in modeling and simulation of integrated circuits. MOR for large scale RC networks resulting from post-layout circuit analysis is still a difficult problem. Elimination based MOR methods has attracted focus. However, in practice, the number of elements in a network may not necessarily reduce during the elimination due to the degradation of sparsity. Given elimination order, in theory there is an optimal elimination, with which the resulting network has minimal elements. In this paper, we propose to find this optimal elimination based on symbolic analysis and statistical analysis. Experimental results show that with such approach the solution time of reduced network can be reduced by a factor of 2-5.
分 类 号:TN391.9[电子电信—物理电子学]
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