异步时钟亚稳态仿真方法  

Simulation methodology for metastability in the asynchronous clocks

作　　者：高文辉[1] 胥志毅[1] 邬天恺[1] 刘文江[1] 仲景尼[1] 

机构地区：[1]南京电子技术研究所,南京210039

出　　处：《信息技术》2012年第10期167-169,共3页Information Technology

摘　　要：当信号跨越时钟域的时候,会带来亚稳态问题,现在通用的做法是两级触发器同步来消除亚稳态。实际电路中在目的寄存器的时钟域获得该信号的时间可能不固定,通常相差一个时钟,提出了一种仿真方法,可以仿真实际电路中这种不确定现象。通过这种方法可以在仿真阶段检查跨时钟域信号设计是否合理。避免实际电路中的这种不稳定带来的功能失效。Cross-clock domain signals come across the phenomenon of metastability.The prevalent way to cope with this problem is the usage of two flip-flops as a synchronizer.However in real circuits the synchronizer does not always gives right answer.The time that the target register receives the change of signal may delay one clock period.This paper proposes a way to simulate this uncertainty.This paper presents a method to check the validity of cross-clock domain signals through the simulation,thus avoiding the failure in real circuit due to this uncertainty.

关 键 词：异步时钟 亚稳态 仿真方法 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]