利用CPLD实现FPGA的快速加载  

FPGA fast loading of configuration files through CPLD

作　　者：张玄[1] 李开航[1] 

机构地区：[1]厦门大学物理学系,福建厦门361005

出　　处：《现代电子技术》2012年第22期163-166,170,共5页Modern Electronics Technique

摘　　要：基于SRAM的FPGA由于其可编程、可升级的特性,被广泛应用于现代通信系统中。由于其易失性,每次上电后都需要重新对FPGA进行加载。随着通信系统复杂度的提高,FPGA配置文件越来越大,加载时间越来越长,严重影响系统的启动时间。为了提高FPGA的加载效率,在此提出一种通过CPLD进行FPGA串行加载的方案。通过验证,该方法既能能提高FPGA加载效率,又能节省CPU和FPGA的GIPO管脚,降低系统启动时间,非常适用于现代复杂通信系统。SRAM-based FPGA is widely used in modern communication systems because of its programmable and scalable features. However, due to its volatile, every time after power on, it should be reloaded. With the improvement of the com- plexity of the communication system, the configuration file of FPGA is getting larger, and the loading time is getting longer. These affect the system＇s start-up time seriously. A scheme of FPGA serial loading through CPLD is presented in this paper to improve loading efficiency of FPGA. The valitation shows that the scheme can not only save the GIPO pins of CPU and FP- GA, but also improve loading efficiency of FPGA and reduce the start-up time of system. It is an ideal method suitable for complex modern communication systems.

关 键 词：CPLD CPU FPGA加载 PS加载 

分 类 号：TN710-34[电子电信—电路与系统]