关键循环到可重构阵列映射中的时序参数分析  

Timing Parameter Analysis of Critical Loop to Reconfigurable Array Mapping

作　　者：朱敏[1] 刘雷波[1] 尹首一[1] 王星[1] 魏少军[1] 

机构地区：[1]清华大学微电子所,北京100084

出　　处：《计算机工程》2012年第22期260-262,266,共4页Computer Engineering

基　　金：国家"863"计划基金资助项目(2009AA011700);国家自然科学基金资助项目(60803018)

摘　　要：通过定义算法关键循环到可重构阵列映射的建立时间、保持时间等核心时序参数,分析存储器带宽有限、算法数据流图拓扑不规则等实际问题,给出配置时序模型的优化算法,提出路径特征等参数的描述形式,为可重构自动编译提供新的处理方式。验证结果表明,在视频算法H.264关键循环deblocking的映射过程中,该优化映射方法使得性能在原有基础上提升43%。Reconfigurable systems are very efficient on computing intensive domains, and critical loops of algorithms can be set up on a reconfigurable array especially. But how to mapping applications is still a hard work which limits the development of reconfigurable technique. This paper proposes a way to define timing models and method to modify the reconfigurable mapping performance. It is meaningful to the compiler designs. Memory wall on a hardware array and data flow graph topology of algorithms are considered, and the setup/hold times of a loop mapping process is also derived. The definition of path＇s timing feature gives a new way to take out a reconfigurable compiler. Verification shows 43% performance improvement is achieved on mapping critical loop deblocking of H.264 decoding to a reconfigurable system.

关 键 词：关键循环 可重构阵列 算法映射 时序模型 阵列建立时间 阵列保持时间 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]