一种高速、高精度全差分采样保持电路的ASIC设计  

An ASIC Design of a High Speed,High Accuracy Sample-and-hold Circuit

作　　者：魏微[1,2] 陆卫国[1,2] 郭海东 王铮[1,2] 赵京伟[1,2] 

机构地区：[1]中国科学院高能物理研究所 [2]核探测与核电子学国家重点实验室 [3]OmniVision Technologies,Inc.Santa Clara,USA,95054

出　　处：《核电子学与探测技术》2012年第8期893-899,共7页Nuclear Electronics & Detection Technology

摘　　要：为了实现新型密集型阵列探测器信号的高速、高密度读出,必须采用专用集成电路技术,利用模数变换器将物理量变换为数字信号后进行串行输出。采样保持电路是模数变换器中的关键单元,决定了整个模数变换过程的性能。论文在国内高能物理领域,首次利用专用集成电路技术,设计实现了一种用于10位、3.3 Msps采样率的逐次逼近ADC的全差分采样保持电路并成功流片。实测结果表明,该设计分别实现了48 dB的SNDR和78 dB的SFDR,达到了预期的设计指标,实现了较高的性能。To fulfill the detectors, application - requirement of the high speed and high density readout of modem pixel and segmented specific integrated dircuits （ASICs） become the necessities. Physical signals are first transformed into analog waves by front - end electronics, and then translated into digital codes thanks to the help of A/D convertors （ADC）, so that serial outputs can be used to further enhance the speed and density of readout. Among all the modules in an ADC, sample - and - hold circuit （S/H） is the crucial one which domi- nates the overall performance of A/D conversion. This work introduces a fully differential S/H circuit, which, for the first time in domestic high energy physics field, is realized in the form of ASIC. Through a successful tape - out, the design achieved a specification for a successive - approximation ADC of 10 bits and 3.3 Msps/ s sampling rate. The measurement results show that, the real chip fully satisfies the preset targets and shows a high performance of an SNDR of 48 dB, and an SFDR of 78 dB, respectively.

关 键 词：采样保持 专用集成电路 逐次逼近 模散转换电路 

分 类 号：TL82[核科学技术—核技术及应用]