基于源耦合逻辑的正交二分频器设计  

Design of quadrature frequency divider based on SCL

作　　者：齐骋[1] 王亮[1] 凌朝东[1] 杨骁[1] 

机构地区：[1]华侨大学信息科学与工程学院,福建厦门361021

出　　处：《微型机与应用》2012年第22期26-28,31,共4页Microcomputer & Its Applications

基　　金：福建省自然科学基金(2010J05135);厦门市科技计划项目(3502Z20113015);华侨大学基本科研业务费专项基金(JB-ZR1128)

摘　　要：设计了一种基于源级耦合结构的正交二分频电路,由两个完全相同的源级耦合D触发器级联构成,交替工作于触发和锁存模式。对传统的源级耦合结构做了适当改进,采用动态负载,通过对PMOS管的开关控制很好地解决了电路工作速度和输出摆幅间的矛盾;且时钟开关PMOS和NMOS采用不同直流偏置,便于低电源电压下直流工作点的选取。采用TSMC 0.18μm RF CMOS工艺进行仿真验证。实验结果表明,分频器在1.92GHz输入时钟频率下能正常实现正交二分频,有较宽的锁定范围,且在3V电源电压下功耗仅为1.15mW。A quadrature frequency divider based on source-coupled-logic is presented in this paper, and designed in TSMC 0.18 μm IIF CMOS leehnology. It eonsists two identical and mutually coupled flip-flops or latches which operate alternatively in flip-ping and la＇,ehed modes at the clock frequency. In this paper, we adopt dynamic load which shall ideally be small during flipping yet large while latched. This carl keep the RC time constant small and make the signal difference large. Also tile PMOS and NMOS switch-es use different bias, that earl be easier to make a exact DC point. The circuit is designed in TSMC 0.18 μm RF CMOS process and dissipates an power of 1.15 mW from a 3 V supply. It can work at 1.92 GHz normally, and has a wide locking range.

关 键 词：正交二分频 源级耦合 动态负载 锁定范围 

分 类 号：TN4[电子电信—微电子学与固体电子学]