基于FPGA的Turbo码译码器的设计  

Design of Turbo Decoder Based on FPGA

作　　者：韦照川[1] 常雪景[1] 蔡成林[1] 孙希延[1] 

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《电视技术》2012年第23期116-120,共5页Video Engineering

基　　金：国家自然科学基金项目(61162007);广西区自然基金重点项目(2012GXNSFDA053027)

摘　　要：主要论述了一种基于FPGA的Turbo码译码器的设计。首先简单介绍了编码器和交织器的原理;然后介绍了基于Max-Log-MAP算法的译码器原理,对分量译码器做了详细论述,给出了各子模块原理和ModelSim仿真图形;最后给出了系统仿真的误码率图形。A design of Turbo decoder is discussed primarily based on FPGA. Firstly, the theory of the coder and the interleaver are described briefly. Secondly, the theory of the decoder based on Max-Log-MAP algorithm is introduced. The component decoder is described in detail and every submodule＇s theory and the simulation graph by ModelSim are given. Finally, the bit error rate graph is presented by the system simulation.

关 键 词：TURBO码 译码 MAX-LOG-MAP算法 现场可编程门阵列 

分 类 号：TN929.5[电子电信—通信与信息系统]