低功耗并行的提升式5/3二维离散小波变换的VLSI架构  

Low Power Parallel VLSI Architecture for Lifting-based 5/3 2-D Discrete Wavelet Transform

作　　者：毛曼卿[1] 王春林[1] 陈卓[1] 刘克刚[1] 

机构地区：[1]武汉大学电子信息学院

出　　处：《电子技术（上海）》2012年第11期21-24,共4页Electronic Technology

摘　　要：离散小波变换需要较大的运算量和运算空间,为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散5/3小波变换的VLSI架构,这种结构同时进行行变换和列变换。文章对于VLSI架构的五大模块(行小波变换运算模块、两个列小波变换模块、FIFO寄存组和系统整体控制模块)的硬件实现给出了相应的方案。在Quartus II 7.2的平台下对于设计的该系统的时序仿真测试结果表明,综合分析后系统最小组合逻辑时延为7.142ns,可达到的最高频率为140.02MHz。时序仿真测试中当系统工作频率为100MHz,数据吞吐率达到773.944Mbit/s。Discrete Wavelet Transform （DWT） needs for intensive computation process and large operation space. In order to increase JEPG2000＇s image compression speed, an architecture, which processes row and column transform simultaneously, for 2-D discrete 5/3 wavelet transform based on lifting scheme is presented in this paper. Also the paper gives the corresponding scheme about the hardware implementation for the five key modules of VLSI architecture （line wavelet transform module, two Column transform modules, FIFO memory buffer and system control module）. The testing results of the timing simulation based on the Quartus II 7.2 platform indicate that the system could get the speed of 140.02MHz, the maximum combinational logic delay of 7.142ns. And the data throughtput is as high as 773.944Mb/s at the system operation frequency of 100MHz.

关 键 词：离散小波变换 提升式算法 低功耗 并行 

分 类 号：TN919.81[电子电信—通信与信息系统]