A digital background calibration algorithm of a pipeline ADC based on output code calculation  

作　　者：邵健健 李玮韬 孙操 李福乐 张春 王志华 

机构地区：[1]Institute of Microelectronics,Tsinghua University

出　　处：《Journal of Semiconductors》2012年第11期110-114,共5页半导体学报（英文版）

摘　　要：This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic.Based on the analysis of the output codes,the calibration logic estimates the bit weight of each stage and corrects the outputs.An experimental 14-bit pipelined ADC is fabricated to verify the algorithm.The results show that INL errors drop from 20 LSB to 1.7 LSB,DNL errors drop from 2 LSB to 0.4 LSB,SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB.The linearity of the pipelined ADC is improved significantly.This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic.Based on the analysis of the output codes,the calibration logic estimates the bit weight of each stage and corrects the outputs.An experimental 14-bit pipelined ADC is fabricated to verify the algorithm.The results show that INL errors drop from 20 LSB to 1.7 LSB,DNL errors drop from 2 LSB to 0.4 LSB,SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB.The linearity of the pipelined ADC is improved significantly.

关 键 词：pipeline ADC output code calculation background calibration 

分 类 号：TN792[电子电信—电路与系统]