A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB  

作　　者：蔡化 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China

出　　处：《Journal of Semiconductors》2012年第11期126-133,共8页半导体学报（英文版）

摘　　要：This paper describes the design of a 14-bit 20 Msps analog-to-digital converter（ADC）,implemented in 0.18μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power.The proposed ADC consumes only 166 mW under 1.8 V supply.A fast background calibration is utilized to ensure the overall ADC linearity.This paper describes the design of a 14-bit 20 Msps analog-to-digital converter（ADC）,implemented in 0.18μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power.The proposed ADC consumes only 166 mW under 1.8 V supply.A fast background calibration is utilized to ensure the overall ADC linearity.

关 键 词：CMOS opamp-sharing low-power and background calibration 

分 类 号：TN792[电子电信—电路与系统] TP368.1[自动化与计算机技术—计算机系统结构]