QPSK中频全数字解调器的研究与FPGA实现  

Research and FPGA realization of all-digital intermediate frequency QPSK demodulator

作　　者：张钰磊[1] 姜生瑞[1] 

机构地区：[1]兰州交通大学电子与信息工程学院,甘肃兰州730070

出　　处：《电子测试》2012年第11期42-47,共6页Electronic Test

摘　　要：基于QPSK调制方式的高效率、低误码率、频谱性能好等特点,本文采用可编程逻辑器件CycloneⅡEP2C70F896C6N成功地实现了QPSK全数字解调的电路的设计。分别在MATLAB软件和Quartus Ⅱ9.0软件中进行了解调器中的核心模块的设计和仿真,同时在各个模块仿真成功的情况下,对整体电路进行了仿真。输入端的信号都为20MHz的中频已调信号,最后准确解调出基带信号。通过比较Quartus II仿真结果和MATLAB仿真结果,解调出来的结果是一致的,这也说明了所设计的解调模块是正确的。在信噪比为10dB时,误码率达到10-3,显然电路的设计能够达到要求的性能指标。It is based on the high efficiency, low error rate, spectral performance characteristics of QPSK modulation. This paper use the programmable logic devices Cyclone ii EP2C70F896C6N successfully realized the circuit design of QPSK full digital demodulation. This paper design and simulation to the demodulators core module in MATLAB software and Quartus II 9 software. After each module is succeed in simulating , the overall circuit is simulated .The input part is same signal that is modulated signal in 20MHz medium frequency, and finally accurate demodulation baseband signal. After compared the simulation results between MATLAB and Quartus II, the same result shows that the design of demonstrate module is correct. When the ratio of signal and noise is 10 dB, the error rate reaches 10 -3 . It is clear that the circuit design can achieve the required performance indicators.

关 键 词：QPSK 解调 FPGA 

分 类 号：TN915.05[电子电信—通信与信息系统]