SHA-2(256,384,512)系列算法的硬件实现  

On the Hardware Implementations of the SHA-2(256,384,512) Hash Function

作　　者：刘政林[1] 董馨[1] 李东方[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《微电子学与计算机》2012年第12期51-54,共4页Microelectronics & Computer

基　　金：国家自然科学基金项目(60973034);新世纪优秀人才支持计划项目(NCET-07-0328)

摘　　要：在同一系统中存在着对安全性要求不同的应用,可能需要对SHA-256、SHA-384、SHA-512算法进行选择,目前大部分研究只是对这几种算法单独地进行了硬件实现.本文提出了一种SHA-2(256,384,512)系列算法的VLSI结构,基于这种结构,根据不同的要求,每一种SHA-2算法都可以单独灵活地执行.本文还对该系列算法和各个独立SHA-2算法的FPGA实现进行了比较,结果表明,在面积较SHA-256实现增加40%,而与SHA-384/512基本相同的情况下,频率可达到74MHz.In a system, applications with different security requirements need selection among algorithm SHA-256, SHA-384, SHA-512. However, these types of algorithms were implemented in hardware separately in current studies. In this paper, a VLSI architecture for the SHA-2 family is proposed, in order to meet the needs of different options. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions （256,384,512） of the SHA--2 standard. The proposed system is compared with the implememation of each hash function in FPGA device. The results show that the frequency of the introduced system can be achieved 74MHz, while the area of the implement only increase 40% over SHA-256 and basically the same as SHA-384/512.

关 键 词：哈希函数 安全性 密码学 SHA-2(256 384 512) 硬件实现 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]