一种低功耗2D DFT芯片的前端设计与验证  

The Front-end Design and Verification of a Low Power 2D DFT Chip

作　　者：谢新辉[1] 唐立军[1] 邓敏[1] 

机构地区：[1]长沙理工大学物理与电子科学学院,湖南长沙410004

出　　处：《微电子学与计算机》2012年第12期166-170,共5页Microelectronics & Computer

基　　金：国家电网公司科技项目(KZ11K15003);湖南省自然科学基金(07JJ3112);国家科技部科技支撑计划课题(2012BAH1704);长沙市科技局科技项目(K0803081-11);湖南省教育厅科研基金项目(07C086)

摘　　要：本文基于Nangate 45nm CMOS开放工艺库,设计了一种适用于数字图像处理的二维离散傅里叶变换(2-Dimensional Discrete Fourier Transform,2DDFT)芯片,并对其进行了前端验证.该芯片采用时域抽取法基-2快速傅里叶算法(Radix-2 Fast Fourier Transform)以及优化的流水线结构,使得设计难度大大降低,处理速度得到较大提升.功能验证和逻辑综合后的结果显示,该芯片能够在250MHz时钟频率下工作,只需延迟1211个时钟周期即开始输出一个由16位单精度定点数构成的32×32位复数矩阵的DFT值,且在0.9V电压下功率为143mW,表明芯片在速度、精度以及功耗上均满足低功耗数字图像处理系统的要求.This paper verifies the front-end design of a 2-Dimensional Discrete Fourier Transform chip which is suitable for digital image processing using Nangate 45nm CMOS open cell library. Both the radix-2 decimation in time FFT algorithm and optimized pipeline structure were chose in the 2D DFT algorithm to lighten the design complexity. The functional simulation and hardware synthesis results show that the chip can work under 250MHz clock and output the DFT results of 32 ~ 32 complex matrix after 1211 clock cycles; the input and output datatype is 16-bit single precision fixed-point number. The power dissipation is only 143mW under voltage of 0. 9 V. The simulation shows that the design can meet with the efficiency, precision and power dissipation requirements in low power digital image processing system.

关 键 词：快速傅里叶变换 流水线结构 数字图像处理芯片 

分 类 号：TN764[电子电信—电路与系统]