A high linearity current mode multiplier/divider with a wide dynamic range  

作　　者：廖鹏飞 罗萍 张波 李肇基 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China

出　　处：《Journal of Semiconductors》2012年第12期62-65,共4页半导体学报（英文版）

基　　金：Project supported by the Important National S&T Special Project of China(Nos.2009ZX01031-003-003,51308020305)

摘　　要：A high linearity current mode multiplier/divider （CMM/D） with a wide dynamic range is presented. The proposed CMM/D is based on the voltage-current characteristic of the diode, thus wide dynamic range is achieved. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature and device parameters of the fabrication process. Furthermore, no extra bias current for all input signals is required and thus power saving is realized. With proper selection of establishing the input terminal, the proposed circuit can perform as a mulfifunction circuit to he operated as a multiplier/divider, without changing its topology. The proposed circuit is implemented in a 0.25μm BCD process and the chip area is 0.26 ~ 0.24 mm2. The simulation and measurement results show that the maximum static linearity error is 4-1.8% and the total harmonic distortion is 0.4% while the input current ranges from 0 to 200 μA.A high linearity current mode multiplier/divider （CMM/D） with a wide dynamic range is presented. The proposed CMM/D is based on the voltage-current characteristic of the diode, thus wide dynamic range is achieved. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature and device parameters of the fabrication process. Furthermore, no extra bias current for all input signals is required and thus power saving is realized. With proper selection of establishing the input terminal, the proposed circuit can perform as a mulfifunction circuit to he operated as a multiplier/divider, without changing its topology. The proposed circuit is implemented in a 0.25μm BCD process and the chip area is 0.26 ~ 0.24 mm2. The simulation and measurement results show that the maximum static linearity error is 4-1.8% and the total harmonic distortion is 0.4% while the input current ranges from 0 to 200 μA.

关 键 词：high linearity current mode multiplier/divider static linearity THD 

分 类 号：TP332.22[自动化与计算机技术—计算机系统结构]