一种Boost型APFC控制芯片的设计与实现  

Design and Implementation of Boost Type Active Power Factor Correction Controller IC

作　　者：代国定[1,2] 马晓辉[1] 欧健[1] 薛超耀[1] 马任月[1] 卢晶[1] 

机构地区：[1]西安电子科技大学电路CAD研究所,陕西西安710071 [2]超高速电路设计与电磁兼容教育部重点实验室,陕西西安710071

出　　处：《西南交通大学学报》2012年第6期1015-1020,共6页Journal of Southwest Jiaotong University

基　　金：国家部委预研基金资助项目(9140A08010208DZ0123)

摘　　要：为抑制谐波对公共电网的污染、提高电能利用率,针对中小功率电器功率因数校正的需要,设计了一种基于Boost型拓扑结构的有源功率因数校正控制芯片.该芯片采用临界导通模式控制,加入总谐波失真优化电路,解决了输入电流过零处的交越失真问题.设计了带双模式过压检测的电压反馈电路,实现了对整个系统的快速瞬态响应和异常保护.整个电路采用CSMC 0.5μm BCD工艺设计,芯片面积仅1.36 mm2.基于该芯片,设计了80 W功率因数校正电路.测试结果表明:在220 V交流输入、满负载条件下,电流THD(总谐波失真)为3.1%,功率因数达0.997,效率为96.8%,表明该芯片很好地实现了功率因数校正功能.A boost type active power factor correction controller based on the critical mode control technology was proposed to restrain harmonic currents and improve the efficiency of electrical power. A total harmonic distortion optimizer circuit was specially integrated to solve the crossover distortion problem that input current is zero. And a voltage feedback circuit with two over-voltage detection modes was designed to achieve fast instantaneous response and unexpected protection. A chip, with an area of only 1.36 mm2, was fabricated by the CSMC 0.5 μm BCD process. A 80 W APFC circuit was constituted based on the chip. The test results under a full load show that the measured power factor is 0.997, the total harmonic distortion of input current is 3.1% and the efficiency is 96.8% to prove that the chip achieves the function of power factor correction.

关 键 词：有源功率因数校正 临界导通模式 总谐波失真 BCD工艺 

分 类 号：TN432[电子电信—微电子学与固体电子学]