基于FPGA的IRFPA图像细节增强与动态压缩处理技术  

IRFPA image detail enhancement and dynamic compression technique based on FPGA

作　　者：范永杰[1,2] 金伟其[1] 刘崇亮[1] 陈艳[1] 刘斌[1] 李家坤[1] 金明磊[1] 

机构地区：[1]北京理工大学光电学院光电成像技术与系统教育部重点实验室,北京100081 [2]昆明理工大学理学院工程数学中心,云南昆明650000

出　　处：《红外与激光工程》2012年第11期3113-3117,共5页Infrared and Laser Engineering

基　　金：国家自然科学基金(60877060)

摘　　要：红外焦平面探测器输出的模拟信号通常采用14 bit AD进行数字化,并进行后续处理,而常用的显示设备只能显示8 bit图像,于是最终显示需要对图像进行压缩,压缩过程直接影响显示效果。与之相关的图像细节增强和动态范围压缩技术亦是当前行业内重点研究的技术。基于已提出的一种细节增强和动态压缩算法,在以Xilinx公司的XC5VLX50T FPGA为核心处理器件的图像处理板上对算法进行了工程实现,算法完全在FPGA片内利用Verilog-HDL编写实现,不占用片外资源,片内占用资源适中,处理延时小于200μs。实际观测试验验证了算法以及实现手段的有效性。The analog video of IRFPA output is usually converted to digital video by using 14 bit AD, and many image processing are based on 14 bit digital video. Most display equipments can only represent image of 8 bit gray levels, therefore, the method of compressing IRFPA origin 14 bit image to 8 bit image greatly affects the performance of display. The technique concerning detail enhancement and dynamic compression is an important research field of infrared technology. An IR images detail enhancement and dynamic compression algorithm was realized on a designed digital processing board which used Xilinx company＇s XC5VLX50T FPGA as a core designed device. The algorithm was totally implemented in the FPGA by using Verilog-HDL language, consuming modest FPGA resource, whith no resources outside FPGA needed. The processing delay of the algorithm was less than 200 μs. The actual observing experiments for differentscenes show that the algorithm and the way of implement are effective.

关 键 词：动态范围压缩 细节增强 热成像 FPGA 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]