基于两倍过采样的60GHz系统并行定时同步  

Twice-oversampling based parallel timing synchronization scheme for 60GHz systems

作　　者：卢大成[1] 肖振宇[1] 张昌明[1] 金德鹏[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《传感器与微系统》2012年第12期48-51,共4页Transducer and Microsystem Technologies

基　　金：国家科技重大专项计划资助项目(2011ZX03004-001-01);国家自然科学基金资助项目(61021001);清华大学自组织科研基金资助项目(20111080992);清华传信研究基金及中兴通信股份有限公司资助项目

摘　　要：随着60 GHz毫米波无线通信技术的成熟,其在无线传感器网络领域占据的地位日益增高。60 GHz通信系统的符号传输速率高达Gbps量级,为了降低系统复杂度,需要尽量减少每个符号的采样点数。此外,由于待处理的符号速率过高,传统串行定时同步方案受工作时钟约束而无法采用。为此,提出一种基于两倍过采样率的FIFO控制式并行定时同步方案,解决了超高速并行定时同步设计时遇到的时钟频率调整问题。设计的并行定时同步方案具有结构简单、实现复杂度低、同步所需时间短和鲁棒性高等优点,对60 GHz毫米波系统全数字解调器的设计具有较强的应用价值。同时,通过Matlab Simulink仿真,验证了提出的并行定时同步方案的可行性。With the maturity of 60 GHz millimeter-wave wireless communications, it plays an increasingly important role in wireless sensor networks. In order to simplify the system complexity, it is necessary to decrease the sampling rate since the symbol transmission rate of 60 GHz communications system is up to Gbps. In addition, due to the high symbol rate, the traditional serial timing synchronization scheme cannot be adopted for the clock constraint. A FIF0 controlled-parallel timing synchronization scheme based on twice-oversampling is proposed, which solves the clock frequency adjustment problem encountered in design of ultra-high-rate parallel timing synchronization. The scheme has the advantages of simple structure, low complexity, short synchronization time, high robustness, et al. thus it has strong value in the design of all-digital demodulator for 60 GHz millimeter-wave systems. Meanwhile, simulation results on the Matlab Simulink platform verify the feasibility of the proposed parallel timing synchronization.

关 键 词：60 GHZ 定时同步 两倍过采样 并行结构 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]