基于模拟余差的7位200MS／S分级折叠式A／D转换器  

A 7-Bit 200-MS/s Subranging Folding A/D Converter Based on Residue of Analogue Quantity

作　　者：王百鸣[1] 洪岳炜[2] 孟晓胜[2] 

机构地区：[1]深圳大学信息工程学院,广东深圳518060 [2]深圳大学光电子学研究所,广东深圳518060

出　　处：《微电子学》2012年第6期823-826,共4页Microelectronics

基　　金：国家自然科学基金资助项目(90407001,60901016)

摘　　要：提出一种基于模拟余差的分级折叠式A/D转换器,对其原理和电路结构进行了分析,阐述了提高A/D转换器性能的关键问题。测试结果表明,设计的A/D转换器转换速率为200MS/s;在输入信号为6.0MHz时,信噪谐波比(SINAD)为45.1dB,有效位数(ENOB)为7.2位。给出了A/D转换器电路的具体结构,以及测试波形和动态性能参数测试结果。A subranging folding A/D converter based on residue of analogue quantity was presented. Operational principle and circuit structure were analyzed. Key issues concerning improvement of performance of the A/D converter was elaborated. Test results showed that the proposed A/D converter achieved a sampling rate of 200 MS/s, an SINAD of 45.1 dB, and an ENOB of 7.2 bits for 6. 0 MHz input signal. Architecture of the proposed ADC was given. Test waveforms and measurement of dynamic parameters were also presented and discussed in detail.

关 键 词：A D转换器 分级 折叠 模拟余差 

分 类 号：TN431[电子电信—微电子学与固体电子学]