基于FPGA的高速数据采集系统的设计与实现  

Design of High Speed Data Acquisition System Based on FPGA

作　　者：常高嘉[1] 冯全源[1] 

机构地区：[1]西南交通大学微电子研究所,成都610031

出　　处：《电子器件》2012年第5期615-618,共4页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(60990320;60990323);国家自然科学基金面上项目(61271090);国家高技术研究发展计划(863计划)项目(2012AA012305)

摘　　要：高速数据采集系统主要由AD、FPGA和DSP组成。该系统的采样精度为12 bit,采样率为100 MSPS。首先介绍了系统中AD部分的两种前端调理电路的设计与实现,并作了对比,然后介绍了AD的时钟电路,说明了基于Verilog的FPGA程序设计过程。通过调试优化后可以在DSP中稳定、纹波较小地读到AD量化后的数据。This paper designed a high-speed data acquisition system consisting of AD,FPGA and DSP.The sampling accuracy is 12 bit,and sampling rate is 100 MSPS.This paper described two kinds of the front-end conditioning circuits and made a comparison between them,also described the clocking circuit of ADC,then introduced the design process of FPGA ＇ s programs based on verilog.After debugging and optimizing,the wave which reads in the DSP is stable and with a low ripple.

关 键 词：数据采样系统 高速 前端调理电路 FPGA 

分 类 号：TP247.2[自动化与计算机技术—检测技术与自动化装置]