一种高电源抑制比全工艺角低温漂CMOS基准电压源  

A bandgap voltage reference with high PSRR and low temperature drift at the all process corners

作　　者：方圆[1] 周凤星[1] 张涛[1] 张迪 

机构地区：[1]武汉科技大学,湖北武汉430080 [2]德鑫微电子公司,湖北武汉430070

出　　处：《电子设计工程》2012年第24期139-142,共4页Electronic Design Engineering

基　　金：湖北省自然科学基金项目(2011CB234);湖北省教育厅科研项目(D20101104)

摘　　要：基于SMIC0.35μm的CMOS工艺,设计了一种高电源抑制比,同时可在全工艺角下的得到低温漂的带隙基准电路。首先采用一个具有高电源抑制比的基准电压,通过电压放大器放大得到稳定的电压,以提供给带隙核心电路作为供电电源,从而提高了电源抑制比。另外,将电路中的关键电阻设置为可调电阻,从而可以改变正温度电压的系数,以适应不同工艺下负温度系数的变化,最终得到在全工艺角下低温漂的基准电压。Cadence virtuoso仿真表明:在27℃下,10 Hz时电源抑制比(PSRR)-109 dB,10 kHz时(PSRR)达到-64 dB;在4 V电源电压下,在-40～80℃范围内的不同工艺角下,温度系数均可达到5.6×10-6V/℃以下。A bandgap voltage reference circuit which has high PSRR and low temperature drift at all Process Corners was presented based on SMIC＇s 0.35μm CMOS process. First, a high PSRR voltage reference is amplified by a voltage amplifier to get a stabilized voltage, which then is provided to bandgap core as power supply, so as to get high PSRR. Besides, set the key resistor tunable to adjust the positive voltage temperature coefficient, so as to meeting the negative voltage temperature coefficient change under different processes, and ultimately getting a bandgap voltage reference with low temperature coefficient at all processe. Cadence virtuoso simulation results showed that the circuit had a PSRR -109 dB （10 Hz）and --64 dB （10 kHz） at 27℃ and a temperature coefficient below 3.2×10^-6/℃ at all processes under 4 V supply voltage from-40-80℃.

关 键 词：带隙基准 电源抑制比 全工艺角低温漂 可修调电阻 

分 类 号：TN432[电子电信—微电子学与固体电子学]