低相噪硅雷达射频频率源的研究与设计  

Research and Design of the Low Phase Noise Frequency Synthesizer with Integrated VCO

作　　者：李旺 唐俊 

机构地区：[1]成都国腾电子技术股份有限公司,成都610041

出　　处：《固体电子学研究与进展》2012年第6期575-578,共4页Research & Progress of SSE

摘　　要：分析了频率源中各个模块的噪声传递函数,确定影响近端噪声的模块分别是鉴频鉴相器-电荷泵(PFD-CP)、分频器;在默认分频器相位噪声为-158dBc/Hz,通过matlab建模推断,需要PFD-CP模块在10kHz频偏处的输入噪声达到-143dBc/Hz,才能实现频率源输出信号在10kHz频偏处相位噪声-107dBc/Hz。采用0.18μmSiGe BiCMOS工艺,设计了整块芯片,着重优化了PFD-CP模块的输入噪声,经过spectre仿真,PFD-CP模块的输入噪声为-146dBc/Hz,经过实测,输出信号在10kHz频偏处相位噪声为-108dBc/Hz,达到设计预期。Based on analysis of the phase noise model of the frequency synthesizer, it is known that the PFD_CP （phase frequency detector and charge pump） noise and the divider noise are the main contributer of the phase noise. By using matlab model if the divider phase noise of --158 dBc/Hz, is default value PFD_CP must attain --143 dBc/Hz at 10 kI-tz offset in order to realize the designed synthesizer phase noise of -107 dBc/Hz. The frequency synthesizer chip has been designed in 0. 18 μm SiGe BiCMOS technology, simulated results by＇ spectre show that charge pump noise is -146 dBc/Hz at 10 kHz. Measured phase noise of the frequency synthesizer is -108 dBc/Hz@10 kHz at 3 GHz.

关 键 词：频率源 鉴频鉴相器 分频器 电荷泵 相位噪声 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN763