基于DVB-S2的通用LDPC编码器的FPGA设计  

Design of Universal LDPC Encoder in FPGA Based on DVB-S2

作　　者：闫国强[1] 王勇[1] 植涌[1] 程伟丽[2] 

机构地区：[1]四川大学电子信息学院,四川成都610065 [2]四川科技职业学院,四川成都611745

出　　处：《电视技术》2013年第1期1-3,7,共4页Video Engineering

摘　　要：针对DVB-S2标准中的LDPC码编码器,提出了一种基于FPGA的通用LDPC编码器设计,该编码器具有多码率通用的特点,并且利用IPCORE构造出多个ROM和RAM,实现了在同一信息位输入时所有与之关联校验位的并行处理,提高了编码速度。经试验测试表明,编码器能够稳定工作,处理速率约为63.371 Mbit/s,满足DVB-S2中不同码率下LDPC编码器的需求。According to the LDPC encoder of DVB-S2 standard,a design scheme for the common LDPC encoder based on FPGA is proposed. This encoder is commonly multi-rate, which is adopted IPCORE structure to generate multiple ROM and RAM, achieving the parallel processing of all associated check bits when an information bit is being input, and increasing the encoding speed. As shown from the test result, the encoder worked stably with processing rate about 63. 371 Mbit/s, which can meet the requirements of LDPC encoder of DVB-S2 standard under different code rates.

关 键 词：DVB-S2 现场可编程门阵列 通用编码器 低密度奇偶校验码 

分 类 号：TN941.4[电子电信—信号与信息处理]