Highly Configurable Floating-Point FFT IP Core with Reusing Method  

作　　者：LIU Sanjun SUN Linjiao LI Shaowu YI Jinqiao MIAO Yuzhuang 

机构地区：[1]School of Information Engineering, Hubei University for Nationalities [2]School of Electronic Engineering and Computer Science,Peking University [3]School of Electronic Engineering and Computer Science, Peking University

出　　处：《Wuhan University Journal of Natural Sciences》2013年第1期59-66,共8页武汉大学学报（自然科学英文版）

基　　金：Supported by the Natural Science Foundation of Hubei Province (2011CDC017)

摘　　要：A highly configurable fast Fourier transform intellec- tual property core （FFT IP core） that can be mounted on Avalon bus ofNios II processor is designed in this paper, by the means of custom-built components in SOPC Builder. Not only the data number can be configured to 2＂ and the data width can be config- ured as integer or floating-point number of 32 bits, but also the number of inner butterfly units is configurable, which can effec- tively resolve the contradiction between speed and hardware re- source occupancy. The IP core is designed by butterfly computing elements of a mixed radix-4 and radix-2 algorithm and applies the in-place addressing scheme and reusing method to reduce hard- ware resources consumption. Functional simulation by Quartus II platform proves that the results calculated by FFT IP core are ac- cordant with the Matlab results. Hardware test on DE2 develop- ment board by timestamp timer demonstrates that the FFT IP core costs only 34.8 μs to achieve FFT of 512 sampled data with preci- sion of 32-bit floating point. It is demonstrated that the IP core has the advantages of feasible configuration, easy use, and high preci- sion.A highly configurable fast Fourier transform intellec- tual property core （FFT IP core） that can be mounted on Avalon bus ofNios II processor is designed in this paper, by the means of custom-built components in SOPC Builder. Not only the data number can be configured to 2＂ and the data width can be config- ured as integer or floating-point number of 32 bits, but also the number of inner butterfly units is configurable, which can effec- tively resolve the contradiction between speed and hardware re- source occupancy. The IP core is designed by butterfly computing elements of a mixed radix-4 and radix-2 algorithm and applies the in-place addressing scheme and reusing method to reduce hard- ware resources consumption. Functional simulation by Quartus II platform proves that the results calculated by FFT IP core are ac- cordant with the Matlab results. Hardware test on DE2 develop- ment board by timestamp timer demonstrates that the FFT IP core costs only 34.8 μs to achieve FFT of 512 sampled data with preci- sion of 32-bit floating point. It is demonstrated that the IP core has the advantages of feasible configuration, easy use, and high preci- sion.

关 键 词：fast Fourier transform （FFT） IP core embeddedsystem in-place SOPC 

分 类 号：TN914.3[电子电信—通信与信息系统]