高速视频系统中一种异步FIFO缓存设计  

A Kind of Asynchronous FIFO Buffer Design of High Speed Video System

作　　者：房国志[1] 王康[2] 

机构地区：[1]哈尔滨理工大学测控技术与仪器黑龙江省高校重点实验室,黑龙江哈尔滨150080 [2]哈尔滨理工大学测控技术与通信工程学院,黑龙江哈尔滨150080

出　　处：《哈尔滨理工大学学报》2012年第6期102-105,共4页Journal of Harbin University of Science and Technology

摘　　要：在数字电视系统中,为了满足系统对高速数据的采集的缓存需求,通过研究FIFO的工作原理,利用FPGA和SDRAM设计了一种高速大容量的异步FIFO.介绍了SDRAM的存储结构及操作方法,阐述了基于SDRAM控制器的异步FIFO的设计方法,结合实际,完成了在数字电视系统中基于FPGA和SDRAM的大容量异步FIFO的设计与实现,有效的解决了数字电视系统中对高速视频处理时的海量缓存问题.In the digital television system,in order to meet the cache needs of high-speed data acquisition,we first research the principle of FIFO,then design a high-speed large-capacity asynchronous FIFO with FPGA and SDRAM.This paper describes the structure and method of operation of the SDRAM memory,describes the method large-capacity asynchronous FIFO based on SDRAM Controller,combined with practical,completion the design and realization of high-capacity asynchronous FIFO based on FPGA and SDRAM in the digital television system,solve the massive cache problems on high-speed video and digital TV system effectively.

关 键 词：数字电视系统 视频 SDRAM控制器 海量缓存 

分 类 号：TP333.1[自动化与计算机技术—计算机系统结构] TN47[自动化与计算机技术—计算机科学与技术]