A novel layout for single event upset mitigation in advanced CMOS SRAM cells  

作　　者：QIN JunRui LI DaWei CHEN ShuMing 

机构地区：[1]School of Computer Science,National University of Defense Technology

出　　处：《Science China(Technological Sciences)》2013年第1期143-147,共5页中国科学（技术科学英文版）

基　　金：supported by the National Natural Science Foundation of China (Grant Nos. 60836004 and 60906014);Hunan Provincial Innovation Foundation For Postgraduate (Grant No. CX2011B026)

摘　　要：A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.

关 键 词：single event upset layout technique SRAM radiation hardening by design 

分 类 号：TN47[电子电信—微电子学与固体电子学]