电能计量芯片Sigma-Delta ADC降采样滤波器设计  

Decimation Filter Design of Electrical Energy Measurement IC Sigma-Delta ADC

作　　者：秦龙[1] 陈光化[1] 刘晶晶[1] 曾为民 

机构地区：[1]上海大学微电子研究与开发中心,上海200072 [2]华润上华科技有限公司,江苏无锡214028

出　　处：《计算机技术与发展》2013年第1期181-184,共4页Computer Technology and Development

基　　金：2011年国家科技重大专项(2011ZX02507)

摘　　要：Sigma-Delta ADC精度高,是电能计量芯片的首选ADC。文中设计了一个应用于电能计量芯片中∑-△ADC的数字抽取滤波器,将∑-△调制器输出的串行比特流信号转换成多位并行输出。该抽取滤波器采样多级抽取结构,由级联积分梳状滤波器(Cascaded Integrator Comb,CIC),半带滤波器(Half Band Filter,HBF)以及FIR补偿滤波器组成。对各级滤波器的阶数、系数进行优秀设计,实现128倍的抽取。对HBF采用有符号正则数编码节(CSD)编码,经优化设计后,在CSMC 0.18um工艺下综合,与传统方法相比,面积减少8%,功耗降低15%。实验结果表明:该方法使抽取滤波器在面积和功耗上都有所改善,且性能完全符合电能计量芯片设计要求。Electrical energy measurement requires high accuracy, Sigma-Delta ADC meets it. It presents a decimator filter that can be used in electrical energy measurement IC for Y^- A ADC, using this decimation will converted the Sigma-Delta modulator signal of the serial bit stream into a number of parallel. The filter consists of a CIC filter,a HBF and a FIR compensation filter. Optimize the order and coef- ficient to realize decimation ratio of 128. In implemention of HBF with CSD code, use CSMC 0.18urn process to synthesis and then found the area is less than 8% ,and power dissipation is less than 15% ,compared with convention method after optimization. Experimental re- sults show the decimation filter has improved in the area and power, and performance in full compliance with the requirements of the ener- gy metering chip.

关 键 词：Sigma—Delta ADC 降采样滤波器 级联积分梳状滤波器 半带滤波器 补偿滤波器 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]