A clock generator for a high-speed high-resolution pipelined A/D converter  

作　　者：赵磊 杨银堂 朱樟明 刘帘羲 

机构地区：[1]School of Microelectronics,Xidian University

出　　处：《Journal of Semiconductors》2013年第2期72-77,共6页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028);the National High-Tech R&D Program of China(No.2009AA01 Z258);the Shaanxi Special Major Technological Innovation Program(No.2009ZKC02-11)

摘　　要：A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop （DLL）, and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 um 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop （DLL）, and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 um 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.

关 键 词：duty cycle stabilizer clock jitter dynamic logic non-overlap clock 

分 类 号：TN792[电子电信—电路与系统]