PDP列芯片200MHz工作频率测试方法研究  

Research on the test method of the 200MHz running frequency of PDP data driver IC

作　　者：华国环[1] 庄华龙[1] 孙伟锋[1] 李智群[1] 

机构地区：[1]东南大学集成电路学院,南京210096

出　　处：《电子测量与仪器学报》2012年第12期1050-1055,共6页Journal of Electronic Measurement and Instrumentation

摘　　要：提出了一种测试PDP列芯片200 MHz工作频率的方法。该方法基于Altera公司中高端的FPGA,利用PLL倍频后的400 MHz内部时钟信号,生成256路PDP列芯片用的200 MHz时钟信号以及2.5 ns的单bit数据信号;通过设计对应的测试接口卡,将FPGA产生的时钟、数据和控制信号提供给PDP列芯片工作;设计目标是通过200 MHz时钟信号的精确移位传输,最终让列芯片的256路高压输出中只有OUT37有频率为568.9 kHz方波信号输出,其他255个输出为恒定高电平;测试结果显示,列芯片的256路高压输出中的确只有OUT37是方波信号,并且频率为567.7 kHz,跟设计值十分接近;该结果表明待测列芯片完全可以工作在200 MHz的时钟频率下,并且数据信号也可以在200 MHz频率下被列芯片正确移位传输。A test method of the 200 MHz running frequency of PDP data driver IC is proposed.The test method is based on advanced FPGA fabricated by Altera Company.The inner 400 MHz signal generated by PLL can be used to cre-ate the 200 MHz clock signal and the 2.5 ns-single-bit data signal,which are the input signals for 256-channels PDP data driver IC.The clock signal,data signal and control signal generated by FPGA can be offered to PDP data driver IC by the test card.The design goal is to verify that only OUT37 among the 256 outputs is Square Wave Signal and the frequency of which is 568.9 kHz by the accurate shift transmission of 200 MHz clock signal.The test results reveal that only OUT37 is Square Wave Signal and the frequency is very close to design goal,which is 567.7 kHz.The test results confirm that the running frequency of clock and data signal of 256-channels PDP data driver IC can reach up to 200 MHz.

关 键 词：PDP列芯片 FPGA VERILOGHDL Full HD 

分 类 号：TP806.1[自动化与计算机技术—检测技术与自动化装置]