基于FPGA的GNSS接收机抗干扰的设计  

Anti-jamming Design of FPGA-based GNSS Receiver

作　　者：何訸[1] 张旭东[1] 

机构地区：[1]电子科技大学,成都611731

出　　处：《火控雷达技术》2012年第4期62-67,共6页Fire Control Radar Technology

基　　金：航空科学基金(20110580002)

摘　　要：由于到达地面的GNSS信号很微弱,导致GNSS接收机极易受到干扰。特别是在作战时,敌方发射的强干扰对GNSS接收机影响很大,如果不施以抗干扰措施,接收机将无法正常工作。本文提出了频域——空域联合抗干扰的技术方案,仿真结果表明频域——空域联合抗干扰的算法比频域抗干扰算法和空域抗干扰算法性能更优越,在FPGA中用Verilog语言实现了该联合域抗干扰的算法。Due to the signal of GNSS arriving at the ous kinds of interference. Especially in the war, the surface is so weak that the GNSS receiver is vulnerable to vari- high power interference transmitted by the enemy would impact the GNSS receiver severely, and the GNSS receiver cannot work normally if we do not use any ant-jamming tech- nique. An anti-jamming scheme uniting frequency domain and space domain is proposed. The simulation result demonstrates that anti-jamming algorithm uniting frequency domain and space domain is better than frequency domain and space domain anti-jamming algorithms, and it can be implemented on FPGA by using Verilog language.

关 键 词：全球导航卫星系统 抗干扰 FPGA 

分 类 号：TN965.5[电子电信—信号与信息处理] TN973.3[电子电信—信息与通信工程]