基于FPGA的多通道高速数据采集系统  

Multichannel High-Speed Data Acquisition System Based on FPGA and USB 2.0

作　　者：吴越[1] 严济鸿[1] 何子述[1] 

机构地区：[1]电子科技大学电子工程学院,四川成都611731

出　　处：《雷达科学与技术》2012年第6期671-676,共6页Radar Science and Technology

摘　　要：为满足某雷达实验平台的需求,设计并实现了一种基于通用串行总线USB的多通道高速数据采集系统。该系统以现场可编程门阵列(FPGA)为核心,利用多组高采样率AD实现多通道高速采集。为保证数据通路的畅通,每通道配备大容量DDR2进行高速数据缓存,并利用DDC降低数据写入速率。系统采用EZ-USB FX2LP系列USB芯片的Slave FIFO接口方式将数据回传至计算机中,由计算机应用程序进行控制、数据采集和波形显示。整个系统由硬件部分、FPGA内部逻辑、USB固件、设备驱动和应用程序构成。经过测试,系统在80MHz采样率下,可以实现中心频率60MHz、带宽10MHz信号的有效采集。测试结果验证了设计方案的正确性和可行性。This paper designs and realizes a USB-based multichannel high-speed data acquisition system to meet the requirements of a radar experiment platform. The system uses FPGA as its control core and em- ploys multiple high sampling rate ADCs to realize multichannel high-speed data acquisition. In order to make sure the data transfer is unblocked, each channel owns a high-capacity DDR2 for high-speed data caching, and DDC to reduce the speed of data writing in. It transfers data to computer with Slave FIFO mode of USB chip of EZ-USB FX2LP family, and has an application program for control, data acquisition and waveform dis- play. The entire system is composed of hardware, logic circuit inside the FPGA, USB firmware, USB device driver and application program. In the test, this system acquires the signal whose centre frequency is 60 MHz and bandwidth is 10 MHz effectively with sample rate at 80 MHz. The test result testifies that this project is correct and valid.

关 键 词：现场可编程门阵列 通用串行总线 数据采集 多通道 高速 

分 类 号：TN957[电子电信—信号与信息处理] TP274.2[电子电信—信息与通信工程]