应用聚类和粗糙集的FPGA底层数据挖掘  

FPGA low level data mining based on cluster and rough set

作　　者：姜大力[1,2] 赵波[3] 王永[1] 李华旺[1] 杨根庆[1] 

机构地区：[1]中国科学院微系统与信息技术研究所,上海200050 [2]中国科学院大学,北京100039 [3]中国科学院长春光学精密机械与物理研究所,吉林长春130022

出　　处：《光学精密工程》2013年第1期233-238,共6页Optics and Precision Engineering

基　　金：空间科学战略性先导科技专项资金资助项目(No.XD04040202)

摘　　要：提出了一种从XDL文件中提取现场可编程门阵列(FPGA)底层逻辑和布线资源的方法。预处理阶段通过正则表达式将原有底层逻辑文件转换为待分析的有层次属性的关系型数据库。数据挖掘阶段则根据各个层次数据内部的特性不同,采用不同的算法进行聚类来得到初步知识。通过粗糙集分析初步知识间的关系和约简属性,得出初步知识间的联系同时进一步提取出决策规则和产生式规则的知识。最后,通过规则验证器和泛化器对提取出的规则进行验证和泛化。实验结果表明,对于大型的FPGA器件,wire的逻辑最高压缩比可以达到2.88×10-4。该方法相对于底层器件有较好的通用性和交互性,适用于对不同器件族FPGA底层信息的知识提取,对深入研究FPGA的拓扑架构,提高对FPGA进行动态重配置的可控性和实现更灵活的重配置很有意义。This paper provides a method to get low level logic and route resources of a Field Program- ming Gate Array（FPGA） from XDL documents. In the preprocess stage, the lowly logic document is transformed to a relational database with different attributes via a regular expression. In the data min- ing stage, different algorithms are adopted to cluster the data to get preliminary knowledge based on the different internal features of each level of the database. By taking a rough set to analyze the pre- liminary knowledge and summarize its attribute, the relation of the preliminary knowledge is obtained and the knowledge for decision rule and production rule is given. Finally, the above rules are validated and generalized through a validator and a generalization device. Experiments show that the highest compressing rate of wire logic can reach 2.88 × 10-4 for a huge FPGA. This method has good versatil- ity and interchangeability and is suitable for acquiring the low level information and knowledge from FPGAs in different apparatus families. The method has signification in exploring the topology frame- work of FPGA, improving controllability for dynamic reconfiguration of FPGA, and achieving more flexibility reconfiguration.

关 键 词：现场可编程门阵列 数据挖掘 粗糙集 聚类 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]