A Nonlinear Dynamic Bandwidth Control Algorithm for Digitally Controlled Phase-Locked Loop  

作　　者：CAI Zhikuang YANG Jun SHI Longxing 

机构地区：[1]National ASIC System Enginering Research Center, Southeast University, Nanjing 210096, China

出　　处：《Chinese Journal of Electronics》2012年第2期384-388,共5页电子学报（英文版）

基　　金：国家自然科学基金（No.60871009）; 航空科学基金（No.2009ZD52045）; 南京航空航天大学基本科研业务费专项科研项目（No.NS2010086）

摘　　要：This paper presents a nonlinear dynamic bandwidth control algorithm for Digitally controlled phase- locked loop （DCPLL）. Because of nonlinear relationship between sensed phase error and feedback clock frequency~ there are many erroneous bandwidth adjustment in the PLL with traditional dynamic bandwidth control algo- rithm. The proposed algorithm adjusts the DCPLL band- width when small phase error has been sensed several times by the phase detector~ thus it avoids unnecessary band- width adjustment. To verify the feasibility of the proposed algorithm, we develop a behavioral model in Matlab. Sim- ulation results show that the DCPLL locking time using the proposed algorithm is reduced to 28.6% to 85.7% compared with the DCPLL employing the traditional algorithm. Fi- nally, a DCPLL is implemented by CSM 0.18μm 1P6M CMOS. The measured results show that the DCPLL with- out the proposed algorithm will spend extra 2.5μs when locking to 550MHz.

关 键 词：Digitally controlled phase-locked loop Dynamic bandwidth control algorithm~ Digital loop filter. 

分 类 号：TN919.8[电子电信—通信与信息系统] TP273[电子电信—信息与通信工程]