应用于MMC-HVDC控制器的改进软件锁相环  

The Improved Software Phase-Locked Loop for Modular Multilevel Converter based HVDC

作　　者：郭敏[1] 赵成勇[1] 张宝顺[1] 刘兴华[1] 翟晓萌[1] 

机构地区：[1]华北电力大学新能源电力系统国家重点实验室,北京昌平区102206

出　　处：《南方电网技术》2012年第6期81-85,共5页Southern Power System Technology

基　　金：国家自然科学基金项目(51177042);"十一五"国家科技支撑计划重大项目(2010BAA01B01)~~

摘　　要：分析了在三相电压不对称情况下传统软件锁相环相位输出产生误差的原因,提出一个改进的单同步坐标变换软件锁相环方法,即通过αβ坐标变换,并延迟T/4周期计算来实现正、负序分量的分离,跟踪三相电压的正序分量以减小误差。基于RTDS搭建了MMC-HVDC一次系统模型,将改进软件锁相环应用于基于FPGA的MMC-HVDC控制器上,采用相关的控制和平衡策略,能有效地调节母线电压和有功功率,说明了改进软件锁相环相位输出的准确性。Analyzing the phase output deviation cause of traditional software phase-locked loop （SPLL） under three-phase asymmetrical voltage, this paper puts forward an improved SPLL model using aft coordinate transform and T/4 shift calculation to realize the separation of the positive and negative sequence components and to track the positive one as to reduce the deviation. Modeling the primary system of modular multilevel converter based HVDC （MMC-HVDC） in RTDS, and using the improved SPLL to the MMC-HVDC controller based on FPGA, and adopting related control and balance strategies, it proves that the controller can effectively adjust the bus voltage and active power, showing that the accuracy of phase output with the improved SPLL is very good.

关 键 词：软件锁相环 模块化多电平电压源型高压直流输电 αβ坐标变换 正序分量 

分 类 号：TM721.1[电气工程—电力系统及自动化]