动态可重构众核处理器仿真平台设计  

Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor

作　　者：韩兴[1] 蒋江[1] 付宇卓[1] 周川[1] 刘子扬[1] 杨凯凯[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《上海交通大学学报》2013年第1期44-48,共5页Journal of Shanghai Jiaotong University

基　　金：国家高技术研究发展计划(863)项目(2009AA012201);IBM共享大学研究项目(SUR201102X)

摘　　要：针对众核处理器,提出了一种基于计算资源划分机制的动态可重构技术.该技术以虚拟计算群为核心,设计了基于硬件支持的动态可重构子网划分和动态可重构的Cache一致性协议以及动态在线的计算资源调度算法,并对系统级多核仿真平台Gem 5进行了扩展.同时,采用实际测试结果验证了众核处理器中动态可重构技术的有效性.结果表明,动态可重构技术可以提高众核处理器的资源利用率,实现动态可重构的Cache一致性协议以及单一矩形物理子网覆盖的子网划分机制.A dynamic reconfiguration technique based on the partitioning of computing resources on many- core processor was introduced. According to the locality principle, both the hardware support, including dynamically reconfigurable sub-netting in NoC and dynamically reconfigurable Cache coherence protocol, and the scheduling algorithm for on-chip computing resources are designed to improve the utilization of the many-core processor. This paper also introduced the simulation platform for dynamically reconfigurable many-core processor, which is developed based on system level simulator Gem 5. The Cache coherence protocol with sub-netting and scheduling algorithm mentioned above was implemented. The simulation re- sult proves the improvement for performance of the many-core processor.

关 键 词：虚拟计算群 众核处理器 可重构 CACHE一致性 仿真平台 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]