CMOS数字电路的速度功耗优化设计  

Optimal Design of High-Speed/Low-Power CMOS Digital Circuits

作　　者：刘淼[1] 周润德[1] 葛元庆[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《微电子学》2000年第4期273-275,共3页Microelectronics

摘　　要：在既定工艺条件下，改善电路性能可以通过改进电路、采用不同的时钟技术以及调整电路的器件尺寸来实现；改进电路，可以提高电路速度，减小或消除时钟偏差问题；选择适当的时钟技术，能够满足功耗、速度或可靠性等方面的不同要求；在优化程序的帮助下，调整器件尺寸能大大减小电路面积并改善电路性能。文中对以上几个方面进行理论分析和计算机模拟，得到有关高速ＣＭＯＳ电路的选择原则和设计方法。In a given process, the circuit performance can be improved by means of circuit technique, clocking strategy and device sizing. By improving the circuit technique, the speed of the circuit can be increased and skew problems can be reduced or eliminated. By selecting the proper clocking strategy, different requirements for pow- er, speed or reliability can be met. Assisted by an optimization program, device sizing can improve circuit speed while reduce the chip area. Theoretical analyses and SPICE simulation of the circuit are made in the above aspects, and the optimal design technique for high-speed, low-power CMOS circuits is achieved.

关 键 词：CMOS 数字电路 高速/低功耗电路 时钟技术 器件尺寸调整 

分 类 号：TN402[电子电信—微电子学与固体电子学]