基于FPGA的MAC层地址表设计与仿真  

Design and simulation of MAC layer address table based on FPGA

作　　者：于翔[1] 郑力明[1] 黄红斌[1] 

机构地区：[1]暨南大学信息科学技术学院电子工程系,广东广州510632

出　　处：《计算机工程与设计》2013年第1期121-125,共5页Computer Engineering and Design

基　　金：广东省自然科学基金项目(8151063201000051);2010年粤港关键领域重点突破基金项目(2010498E12)

摘　　要：为解决高速以太网链路接口中软件方式实现的MAC层地址表机制在处理效率上受到制约的问题,提出了一种基于FPGA(现场可编程门阵列)硬件电路方式实现以太网交换机中MAC地址表的查找,学习和老化。该方法采用hashing算法建立地址表项索引值与MAC地址之间的对应关系,完成满足平均时间复杂度为O(1)的地址查找。由于实际交换机中地址表容量有限,地址学习只能是MAC地址的子集,通过优化hashing函数降低地址冲突发生的概率以及设计一种地址老化机制提高地址表查找能力。仿真结果表明,地址表机制采用硬件电路方式实现比软件方式处理效率更高。To deal with the problem that fast Ethernet link in the realization of software interface way MAC layer address table mechanism in the treatment efficiency is limited, a hardware circuit based on FPGA means is proposed to realize the Ethernet MAC address table in the searching, learning and aging. Hashing algorithm is employed to establish the corresponding relations between address table item index value and MAC address, the average time complexity of search for address table meet 0 （1）. Due to the limited capacity address table, address learning is only MAC address of subset, the probability of address conflict is reduced through the optimization of hashing function, and a address aging mechanism is designed to improve address table lookup ability. Results of the simulation indicated Address table mechanism using hardware circuit way realization way is higher than software processing efficiency.

关 键 词：FPGA 以太网交换机 地址表 hashing算法 地址冲突 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]