嵌入式AES加密存储器的硬件实现  

Implementation of Embedded AES Encryption Algorithm in Hardware

作　　者：冯妮[1,2] 张会新[1,2] 卢一男[1,2] 刘文怡[1,2] 

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室,山西太原030051 [2]中北大学电子测试技术重点实验室,山西太原030051

出　　处：《电视技术》2013年第3期59-61,共3页Video Engineering

基　　金：国家自然科学基金项目(61004127)

摘　　要：介绍了一种基于FPGA的AES硬件加密系统,该系统实现了电子数据的加密及存储。详细说明了AES加密算法的FPGA架构,AES核心算法的接口时序设计,AES加密存储器的硬件设计以及算法验证。硬件加密较之软件加密有实时性高、数据量大以及性能好的特点。FPGA开发周期短的特点与AES灵敏性好、实现效率高、安全性能高的优势相辅相成,为需要保密的电子数据提供更加可靠的保证。An AES hardware encryption system which achieves the target data encryption based on FPGA is introduced in this paper. The overall struc- ture of AES encryption algorithm, the interface timing design of the core algorithm, hardware design of AES encryption memory and algorithm verification are described in detail. Hardware encryption, than software encryption, has the characteristics of real-time, large volumes of data and good perform- ance. FPGA has a short development cycle, and AES has some advantages of good sensitivity, high efficiency and high safety performance. They comple- mentary provide a more reliable guarantee for the confidential and electronic data.

关 键 词：AES FPGA 数据加密 加密存储器 

分 类 号：TN91[电子电信—通信与信息系统]