用于碲锌镉探测器前端读出电路的SAR ADC设计  

Design of SAR ADC for Front-End Readout Circuits of CZT Detector

作　　者：刘永波[1] 魏廷存[1] 曾蕙明[1] 詹思维[1] 

机构地区：[1]西北工业大学计算机学院,陕西西安710065

出　　处：《微电子学与计算机》2013年第2期33-37,共5页Microelectronics & Computer

基　　金：国家重大科学仪器设备开发专项(2011YQ040082)

摘　　要：针对碲锌镉探测器前端读出电路要求低功耗、低噪声、高精度的特点,设计了一种12-bit、1Ms/s的逐次逼近式模数转换器(SAR ADC).该模数转换器由数模转换器(DAC)和比较器等组成.其中DAC采用电荷按比例缩放结构,利用电荷守恒原理,提高了缩放电容的匹配精度.比较器采用多级预放大器级联的动态锁存器结构,采用输出失调校准技术提高了比较器的精度.整个电路采用TSMC 0.18μm 1P6MCMOS混合工艺进行设计和实现.仿真结果表明,在1MHz的采样率、输入为97KHz正弦信号下,SAR ADC的DNL为-0.1/0.37LSB,INL为-0.44/0.32LSB,SNR为65.33dB,ENOB为10.55bit,功耗为1.17mW,满足了系统的设计要求.Based on the low-power, low-noise and high-precision features of front-end readout circuits for CZT detector, a 12- bit, 1Msps successive approximation register analog- to- digital converter （SAR ADC） is designed. The ADC consists of digital- to- analog converter （DAC）, comparator, and so on. The DAC is implemented using charge scaling technique and principle of charge conservation, thus the matching accuracy of the scaling capacitor is improved. The comparator is multi-stage pre-amplifier and dynamic latch cascade structure; its offset error is minimized by using output offset calibration technique. The circuit is implemented and simulated in TSMC 0. 18μm mixed signal CMOS technology. Testing results show that, SAR ADC has -0. 1/0. 37 LSB DNL, -0. 44/0.32 LSB INL, 65. 33dB SNR, 10. 55- bit ENOB and 1. 17mW power consumption. The performances meet the requirements of the front-end readout circuits.

关 键 词：碲锌镉探测器 前端读出电路 低功耗 SAR ADC 比较器 

分 类 号：TN492[电子电信—微电子学与固体电子学]