MOS电流模逻辑加法器结构设计  

The Structure Design of MOS Current Mode Logic Adder

作　　者：梁蓓[1,2] 马奎[1,2] 傅兴华[1,2] 

机构地区：[1]贵州大学电子科学系,贵州贵阳550025 [2]贵州大学微纳电子技术重点实验室,贵州贵阳550025

出　　处：《微电子学与计算机》2013年第2期60-64,共5页Microelectronics & Computer

基　　金：贵州省重点实验室建设计划项目(Z[2010]4006)

摘　　要：为克服传统静态CMOS电路在高频工作时的缺陷,引入了MOS电流模逻辑(MOS Current Mode Logic,MCML)电路.MCML电路是一种差分对称结构逻辑电路,与传统的CMOS电路比较,在高频段工作时功耗相对较低,具有典型的高速低功耗特性.在对MCML电路的开关条件以及具有不同输入端的MCML逻辑门电路进行分析后,提出了实现MCML加法器的两种电路结构,并给出了不同结构的应用条件.仿真结果验证了电路结构设计的有效性.In order to overcome the defect of conventional static CMOS circuits at high frequency, MOS current mode logic circuits were introduced. MOS current mode logic is a kind of differential symmetric logic circuits. Its power consumption is relatively low at high frequency compared to conventional CMOS logic, and it has typical high speed and low power character. MOS current mode logic dreuits with different input terminal were analyzed, then two circuit structures were proposed to realize MOS current mode logic full adder and the application were given for different circuit structure. The simulation results verify the effectiveness of circuit structure.

关 键 词：MCML 高速低功耗电路 加法器结构 差分逻辑电路 

分 类 号：TN403[电子电信—微电子学与固体电子学]