Novel N-hit single event transient mitigation technique via open guard transistor in 65 nm bulk CMOS process  

作　　者：HUANG PengCheng CHEN ShuMing CHEN JianJun LIU BiWei 

机构地区：[1]School of Computer Science,National University of Defense Technology

出　　处：《Science China(Technological Sciences)》2013年第2期271-279,共9页中国科学（技术科学英文版）

基　　金：supported by the National Natural Science Foundation of China (Grant Nos. 60836004 and 61006070)

摘　　要：In this paper,we proposed a new n-channel MOS single event transient(SET) mitigation technique,which is called the open guard transistor(OGT) technique.This hardening scheme is compared with several classical n-channel MOS hardening structures through 3-D TCAD simulations.The results show that this scheme presents about 35% improvements over the unhardened scheme for mitigating the SET pulse,and its upgrade,the 2-fringe scheme,takes on even more than 50% improvements over the unhardened one.This makes significant sense for the semi-conductor device reliability.

关 键 词：single event transient （SET） open guard transistor （OGT） charge collection hardening efficiency. 

分 类 号：TB383.1[一般工业技术—材料科学与工程]