Parallel architecture and optimization for discrete-event simulation of spike neural networks  

作　　者：TANG YuHua ZHANG BaiDa WU JunJie HU TianJiang ZHOU Jing LIU FuDong 

机构地区：[1]Department of Computer Science and Technology,School of Computer,National University of Defense Technology [2]State Key Laboratory of High Performance Computing,National University of Defense Technology [3]College of Mechatronic Engineering and Automation,National University of Defense Technology

出　　处：《Science China(Technological Sciences)》2013年第2期509-517,共9页中国科学（技术科学英文版）

基　　金：supported by the National Natural Science Foundation of China (Grant Nos. 61003082,60921062,61005077)

摘　　要：Spike neural networks are inspired by animal brains,and outperform traditional neural networks on complicated tasks.However,spike neural networks are usually used on a large scale,and they cannot be computed on commercial,off-the-shelf computers.A parallel architecture is proposed and developed for discrete-event simulations of spike neural networks.Furthermore,mechanisms for both parallelism degree estimation and dynamic load balance are emphasized with theoretical and computational analysis.Simulation results show the effectiveness of the proposed parallelized spike neural network system and its corresponding support components.

关 键 词：spike neural network discrete event simulation intelligent parallelization framework 

分 类 号：TP338.6[自动化与计算机技术—计算机系统结构] TP183[自动化与计算机技术—计算机科学与技术]