超高符号率数字均衡技术研究与实现  

Research and implementation of digital equalizer technology with super high-symbol-rate

作　　者：陈晖[1,2] 郝志松[2] 王正[2] 

机构地区：[1]西安电子科技大学,西安710071 [2]中国电子科技集团公司第54研究所,石家庄050081

出　　处：《电子测量与仪器学报》2013年第1期26-31,共6页Journal of Electronic Measurement and Instrumentation

摘　　要：符号传输速率超过500 M波特的超高速数据传输系统中,需利用均衡技术来减小信道失真对信号的影响。通过改进并行横向线性结构和流水乘加等方式,解决CMOS数字电路的时钟速率受限的问题,设计了传输速率超过500 M波特的数字均衡器。经实验测试,该均衡器可将高速数据传输系统的误码率性能提高2 dB。Equalizer is used to reduce the effect of channel distortion in super high-symbol-rate communication system, in which the symbol rates are higher than 500 M bauds. An equalizer, in which the symbol rates excess 500 M bauds, is de- signed by utilizing improved parallel structure and pipelining multiplication-add structure, and the difficulty that the clock rate of CMOS is limited is solved. The experimental test shows that the equalizer can improve BER of higher date trans- mission system by 2 dB in laboratory test.

关 键 词：高符号率信号 500 M波特 数字均衡器 横向线性结构 

分 类 号：TN91[电子电信—通信与信息系统]