一种提高电源抑制率的线性稳压器设计  

A Low Drop-out Voltage Regulator with Improved PSRR

作　　者：吴勤[1] 李巍[1] 李宁[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2012年第6期734-739,750,共7页Journal of Fudan University：Natural Science

基　　金：国家自然科学基金资助项目(61176029)

摘　　要：提出了一种高电源抑制率的低压降线性稳压器.该线性稳压器采用基于二极管负载的跨导运算放大器消除电流补偿型带隙基准中电流纹波;通过自给偏压的方式提高静态工作点的稳定性.在TSMC 0.13μmCMOS工艺下进行了流片,测试结果表明,最小输入电压为1.313V,稳定输出电压为1.2V,最大负载电流为70mA;在满负载时,测得100Hz和10kHz时的电源波纹抑制率(PSRR)分别为-65dB和-68dB,功耗电流为93μA,电源效率为91%;核心芯片面积为0.034mm2.An approach based on DCL-OTA with self-biasing is proposed to improve the power supply ripple rejection（PSRR） of the low drop-out（LDO） voltage regulator.The power supply ripple of the current compensated bandgap voltage reference is substantially reduced by DCL-OTA,and the bias circuitry is simplified with improved stability by self-biasing.This approach is implemented and tested in TSMC 0.13μm CMOS process.The results show that the effective minimum input voltage is 1.313V with the regulated output voltage of 1.2V and maximum loading current of 70mA.The PSRR at 100Hz and 10kHz are-65dB and-68dB,respectively,where the ground current is 93μA with power efficiency of 91% under full loading condition.The active chip area is 0.034mm2.

关 键 词：低压降线性稳压器 纹波抑制率 带隙基准 二极管负载的跨导运算放大器 自给偏置 

分 类 号：TN402[电子电信—微电子学与固体电子学]