利用PLL减小时钟前沿抖动的研究  

Research on Reducing Leading-edge Jitter of Clock Signal Based on PLL

作　　者：吴俊晨[1] 任文成[1] 徐志平[2] 

机构地区：[1]中国电子科技集团公司第五十四研究所 [2]中国人民解放军96275部队

出　　处：《无线电工程》2013年第2期52-54,共3页Radio Engineering

摘　　要：针对通信系统数字信号处理中的时钟前沿抖动问题,给出时钟时域抖动和漂移的定义。在推导时域抖动和频域相位噪声关系式的基础上,对时钟的前沿抖动进行了测量和分析,指出偏离载波远端的相位噪声是构成抖动的主要因素。研究通过窄带锁相环(PLL)提纯时钟的方法,给出了提纯PLL的具体设计过程中主要环路参数:阻尼系数ξ和自然角频率ωn的选取和计算过程,说明设计过程中的注意事项。实现了对高抖动时钟信号的提纯。To address the issue of clock leading-edge jitter in digital signal processing of communication systems, the definitions of clock jitter in time domain and drift are given. Measurements and analysis of leading-edge jitter are implemented based on the rela- tionship between jitter in time domain and phase noise in frequency domain. And it is indicated that the phase noise located far away from the carrier turns out to be the main influencing factor to jitter. The method of using narrow band PLL for clock signal extraction is studied, and the loop parameter selection and computation in the design such as damping coefficient and radial angle are provided. Some notifications in the design are introduced. And the extraction of high -jitter clock signal is realized.

关 键 词：相位噪声 环路参数 前沿抖动 PLL 

分 类 号：TN911.8[电子电信—通信与信息系统]