性能均衡PLL频率合成器的研制  

Development of PLL frequency synthesizer with balanced performance

作　　者：何其波[1] 占腊民[1] 吴国安[1] 朱普庆[1] 

机构地区：[1]华中科技大学光学与电子信息学院,湖北武汉430074

出　　处：《现代电子技术》2013年第5期63-66,共4页Modern Electronics Technique

基　　金：国家自然青年科学基金项目资助(61001012);华中科技大学国防科研自主创新基金(2011);中央高校基本科研业务费专项资金资助

摘　　要：阐述了PLL频率合成器的重要应用及其相对于DDS和DAS频率合成器的优势与不足。在对PLL三个重要参数论述的基础上,提出了制作性能均衡PLL频率合成器的思路。同时设计了一个L波段的频率合成器,在频偏10 kHz时相位噪声为-102 dBc/Hz,杂散抑制为-71 dBc,跳频时间为6μs。证明了这种思路的可行性。The paper presents important applications of PLL synthesizer and its advantages and disadvantages relative to DDS and DAS synthesizer. On the basis of discussion, on PLL＇s structure and its three important parameters, the paper summa- rizes the basic idea about the development of PLL frequency synthesizer with balanced performance. And at the same time, a L- band frequency synthesizer with good function is designed and produced. The phase noise is -102 dBc/Hz when frequency devia- tion is 10 kHz. The spurious suppression equals to -71 dBc, while the hopping time is 6 Ixs. The research result verifies the fea- sibility of the method.

关 键 词：PLL 相位噪声 杂散抑制 跳频时间 性能均衡 

分 类 号：TN74-34[电子电信—电路与系统]