12位200MS/s交织A/D转换器设计  

Design of a 12-Bit 200 MS/s Time-Interleaved A/D Converter

作　　者：程华斌[1] 魏琦[1] 赵南[1] 杨华中[1] 

机构地区：[1]清华大学电子工程系电路与系统研究所,北京100084

出　　处：《微电子学》2013年第1期5-9,共5页Microelectronics

基　　金：国家科技重大专项(2010ZX03006-003-01);中国博士后科学基金资助项目(20100480258)

摘　　要：介绍了一个面向3G/4GLTE通信及雷达等应用的12位200MS/s的高速低功耗A/D转换器(ADC)。采用交织运放共享技术,可节省功耗,同时减小不同通道之间的增益失配、失调失配和带宽失配,提高ADC的性能。为了提高ADC的高频性能并避免时钟采样偏差带来的两路通道失配问题,采用一个工作在200 MS/s采样频率的统一的采样保持电路。芯片采用HJTC0.18μm 1P6MCMOS的工艺制造,核心电路面积为1.6×4(mm2),电源电压2.0V。流片测试结果表明,在4.9MHz的输入频率下,无杂散动态范围(SFDR)为83.1dB,信号噪声失真比(SNDR)为59.6dB,模拟核心电流为120mA,FOM1和FOM2值仅为0.08pJ/step和1.25pJ/step。A 12-bit 200-MS/s analog-to-digital converter for 4G communication and radar systems was presented.In this ADC,time-interleaved and op-amp sharing technology to reduce power consumption,and decrease gain-mismatch,offset-mismatch and bandwidth-mismatch effects as well.To improve high frequency performance and prevent time-skew problems,an SHA operating at 200 MHz was adopted,which contained a high gain and bandwidth opamp.Fabricated in 0.18 μm HJTC 1P6M CMOS process,the core circuit occupied a chip area of 1.6 mm×4 mm.Test results showed that the ADC had an SFDR of 83.1 dB and SNDR of 59.6 dB for an fin of 4.9 MHz,while the core-analog circuit only consumed 120 mA of current from 2.0 V supply.The FOM1 and FOM2 were as low as 0.08 pJ/step and 1.25 pJ/step.

关 键 词：模数转换器 交织 运放共享 数字校正 

分 类 号：TN792[电子电信—电路与系统]