基于CORDIC算法数字下变频的FPGA实现  

The FPGA Implementation of Digital Down Conversion Based on the CORDIC Algorithm

作　　者：任全会[1] 于彦峰[1] 

机构地区：[1]郑州铁路职业技术学院,郑州450052

出　　处：《电测与仪表》2013年第1期117-120,共4页Electrical Measurement & Instrumentation

摘　　要：介绍了基于CORDIC算法数字下变频的FPGA实现,此种方法能同时完成NCO的功能和混频器功能。可以解决基于查找表的DDS实现数字下变频占用FPGA中的乘法器和大量的ROM资源以及输出频谱杂散较大的问题。介绍了CORDIC算法的基本原理,论述了基于CORDIC算法数字下变频结构原理和FPGA实现的具体方法。还在Quartus Ⅱ和Modelsim平台上综合并对滤波器和系统进行功能和时序的仿真。测试结果证明,该方案正确,且有效节省FPGA硬件资源。The FPGA implementation of digital down convert based on the CORDIC algorithm is introduced. The meth- od can also complete the NCO function and mixer function. The shortcoming such as occupying FPGA multiplier and a lot of resources of ROM, outputting spectrum spurious larger, can be overcoming. The article describes the princi- ples of the CORDIC algorithm, and discusses the digital down-conversion architecture principle based on the CORDIC algorithm and the specific methods of the＇FPGA implementation. The method simulates filter and system for function and timing in the Quartus II and Modelsim platform. The test shows that the program correctly, and effectively save the FPGA hardware resources.

关 键 词：CORDIC FPGA 数字下变频 

分 类 号：TM933[电气工程—电力电子与电力传动]