基于FPGA的内置并行CRC校验的UART  

Implementation of UART with Parallel CRC Based on FPGA

作　　者：张增波 陈仲林 肖刘[1,2] 

机构地区：[1]中科院研究生院 [2]中科院电子学研究所,北京100190

出　　处：《自动化与仪表》2013年第2期30-32,40,共4页Automation & Instrumentation

摘　　要：基于串行异步收发器(UART)的通信中经常用到循环冗余校验(CRC),常见的CRC校验电路多为串行校验,校验所需时钟周期较多,基于查找表或输入矩阵转换的并行算法,需要存储余数表,占用大量的硬件资源。该文利用输入和校验多项式的逻辑关系,成功地将基于字节的并行CRC校验算法运用于UART控制器中,在Xilinx公司的可编程门阵列(FPGA)芯片上验证通过,可实现连续多个字节校验。校验一个bit需要1/8时钟周期,降低了校验所需时钟频率,提高了通信的效率,保证了通信的可靠性。In data communication based on universal asynchronous receiver and transmitter （UART）,cyclic redundancy cod,or CRC,is usually used. The familiar CRC circuits are serial,this kind circuit takes one cycle per bit. Parallel arithmetic based of look-up table or converted input matrix requires mounts of memories to storage the residue data. Take up a lot of hordware resources. The method here utilizes the logic relationship between input and residues arc brought to UART controller. It was implemented on field programmable gate array （FPGA）from Xilinx. It takes only eighth cycles,reduces frequency of verification,improves the efficiency of communication,guarantees the reliability of communication.

关 键 词：可编程门阵列 循环冗余校验 并行计算 同步校验 VHD L 串行异步收发器 

分 类 号：TN91[电子电信—通信与信息系统]