SDH中E3复用/解复用系统的FPGA实现  

Implementation of E3 multiplexing/demultiplexing system in SDH based on FPGA

作　　者：胡辽林[1] 刘雪峰[1] 

机构地区：[1]西安理工大学机械与精密仪器工程学院,西安710048

出　　处：《光通信技术》2013年第2期44-46,共3页Optical Communication Technology

基　　金：陕西省教育厅科学研究计划(2010JK716)资助

摘　　要：基于FPGA设计了SDH中E3信号复用/解复用系统,包括HDB3编/译码模块、码速调整模块、映射/解映射模块、定位/解定位模块和复用/解复用模块等。在QuartusⅡ9.0中进行了仿真、综合、布局布线和时序仿真,直至各部分功能分别实现,并在Altera公司的Cyclone第四代产品EP4CE115F29C7N上验证了其正确性。用SDH分析仪ANT-5对设计结果进行了一周的测试,误码为0,说明设计基本正确。E3 multiplexing/demultiplexing system in SDH is designed based on FPGA, including HDB3 cod- ing and decoding, code rates adjustment,mapping/demapping, location/delocation, multiplexing/demultiplex- ing. Then, function simulation, synthesis, layout and timing simulation are conducted through Quartus II 9.0 until the functions have been realized,the designed results are verified by the fourth generation of Altera＇s Cy- clone EP4CEl15F29C7N. We use SDH analyzer （ANT-5） to test the designed multiplexing/demultiplexing system, measurement time is one week, the tested results show that our designs are correct.

关 键 词：同步数字系列 现场可编程门阵列 E3 复用 解复用 

分 类 号：TN914.3[电子电信—通信与信息系统]